DSD LAB

Experiment 1: (Design and Simulation of boolean functions using Verilog HDL. Hardware implementation of a Boolean function in sum of products and product of sums expressions using universal gates.)

RTL Schematic:

SOP:
module SOP ( output F, input A, input B, input C );
wire w1,w2,w3 ; 
nand NAND1 (w1,A,A) ; 
nand NAND2 (w2,A,B) ; 
nand NAND3 (w3,w1,C) ; 
nand NAND4 (F,w2,w3) ; 
endmodule
                        
POS:
module POS ( output F, input A, input B, input C ) ; 
wire w1,w2,w3 ;
nor NOR1 (w1,A,A) ; 
nor NOR2 (w2,A,C) ; 
nor NOR3 (w3,w1,B) ; 
nor NOR4 (F,w2,w3) ; 
endmodule

Testbench Simulation:

SOP:
module SOP_tb();
reg A,B,C;
wire F;
SOP SOP1(F,A,B,C);
initial begin
A=0;B=0;C=0;
#10 A=0;B=0;C=1;
#10 A=0;B=1;C=0;
#10 A=0;B=1;C=1;
#10 A=1;B=0;C=0;
#10 A=1;B=0;C=1;
#10 A=1;B=1;C=0;
#10 A=1;B=1;C=1;
#10 $finish;
end
endmodule

POS:
module POS_tb();
reg A,B,C;
wire F;
POS POS1(F,A,B,C);
initial begin
A=0;B=0;C=0;
#10 A=0;B=0;C=1;
#10 A=0;B=1;C=0;
#10 A=0;B=1;C=1;
#10 A=1;B=0;C=0;
#10 A=1;B=0;C=1;
#10 A=1;B=1;C=0;
#10 A=1;B=1;C=1;
#10 $finish;
end
endmodule

Experiment 2:(Design and Simulation of Full Adder circuit using Verilog HDL. Hardware implementation of Full Adder circuit using logic gates.)

RTL Schematic:

module Full_Adder ( output Cout, output Sum, input A, input B,input Cin) ;
wire w0,w1,w2 ;
xor XOR1 (w0,A,B) ;
and AND1 (w1,A,B) ;
xor XOR2 (Sum,w0,Cin) ;
and AND2 (w2,w0,Cin) ;
or OR1 (Cout,w1,w2) ;
endmodule

Testbench Simulation:

module Full_Adder_tb();
reg A,B,Cin;
wire Cout,Sum;
Full_Adder Full_Adder1(Cout,Sum,A,B,Cin);
initial begin
A=0;B=0;Cin=0;
#10 A=0;B=0;Cin=1;
#10 A=0;B=1;Cin=0;
#10 A=0;B=1;Cin=1;
#10 A=1;B=0;Cin=0;
#10 A=1;B=0;Cin=1;
#10 A=1;B=1;Cin=0;
#10 A=1;B=1;Cin=1;
#10 $finish;
end
endmodule

Experiment 3:(Design and Simulation of 3 line to 8 line active high decoder using Verilog HDL.Realization of 3 variable Boolean function using active low decoder)

RTL Schematic:

module Decoder_three_to_eight ( output D0, output D1, output D2, outputD3,output D4, output D5,output D6, outputD7,input I2, input I1, input I0 ) ;
wire w0,w1,w2;
not NOT1 (w0,I0);
not NOT2 (w1,I1);
not NOT3 (w2,I2);
and AND1 (D0,w2,w1,w0);
and AND2 (D1,w2,w1,I0);
and AND3 (D2,w2,I1,w0);
and AND4 (D3,w2,I1,I0);
and AND5 (D4,I2,w1,w0);
and AND6 (D5,I2,w1,I0);
and AND7 (D6,I2,I1,w0);
and AND8 (D7,I2,I1,I0);
endmodule

Testbench Simulation:

module Decoder_three_to_eight_tb();
reg I2,I1,I0;
wire D0,D1,D2,D3,D4,D5,D6,D7;
Decoder_three_to_eight Decoder_three_to_eight1(D0,D1,D2,D3,D4,D5,D6,D7,I2,I1,I0);
initial begin
I2=0;I1=0;I0=0;
#10 I2=0;I1=0;I0=1;
#10 I2=0;I1=1;I0=0;
#10 I2=0;I1=1;I0=1;
#10 I2=1;I1=0;I0=0;
#10 I2=1;I1=0;I0=1;
#10 I2=1;I1=1;I0=0;
#10 I2=1;I1=1;I0=1;
#10 $finish;
end
endmodule

Experiment 4:(Design and Simulation of 8-to-1-line Multiplexer using Verilog HDL. Generation of 4 variable logic function using 8-to-1-line Multiplexer)

RTL Schematic:

module MUX_eight_to_one ( output F, input S2, input S1, input S0, input I7, inputI6,input I5,input I4, input I3, input I2, input I1, inputI0);wire w0,w1,w2,w3,w4,w5,w6,w7,w8,w9,w10 ;
not NOT1 (w0,S0) ;
not NOT2 (w1,S1) ;
not NOT3 (w2,S2) ;
and AND1 (w3,I0,w2,w1,w0) ;
and AND2 (w4,I1,w2,w1,S0) ;
and AND3 (w5,I2,w2,S1,w0) ;
and AND4 (w6,I3,w2,S1,S0) ;
and AND5 (w7,I4,S2,w1,w0) ;
and AND6 (w8,I5,S2,w1,S0) ;
and AND7 (w9,I6,S2,S1,w0) ;
and AND8 (w10,I7,S2,S1,S0) ;
or OR1 (F,w3,w4,w5,w6,w7,w8,w9,w10) ;
endmodule

Testbench Simulation:

module MUX_eight_to_one_tb();
reg S2,S1,S0,I7,I6,I5,I4,I3,I2,I1,I0;
wire F;
MUX_eight_to_one MUX_eight_to_one1(F,S2,S1,S0,I7,I6,I5,I4,I3,I2,I1,I0);
initial begin
S2=0;S1=0;S0=0;I7=0;I6=0;I5=0;I4=0;I3=0;I2=0;I1=0;I0=0;
#10 S2=0;S1=0;S0=0;I7=0;I6=0;I5=0;I4=0;I3=0;I2=0;I1=0;I0=1;
#10 S2=0;S1=0;S0=0;I7=0;I6=0;I5=0;I4=0;I3=0;I2=1;I1=0;I0=0;
#10 S2=0;S1=0;S0=0;I7=0;I6=0;I5=0;I4=0;I3=0;I2=1;I1=0;I0=1;
#10 S2=0;S1=0;S0=0;I7=0;I6=0;I5=0;I4=0;I3=0;I2=1;I1=1;I0=0;
#10 S2=0;S1=0;S0=0;I7=0;I6=0;I5=0;I4=0;I3=0;I2=1;I1=1;I0=1;
#10 S2=0;S1=0;S0=0;I7=0;I6=0;I5=0;I4=1;I3=0;I2=0;I1=0;I0=0;
#10 S2=0;S1=0;S0=0;I7=0;I6=0;I5=0;I4=1;I3=0;I2=0;I1=0;I0=1;
#10 $finish;
end
endmodule

Experiment 5:(Design and simulate JK flip-flop and D flip-flop using Verilog behavioral modeling. Designing of JK flip-flop using D flip-flop and 2X1 Multiplexer.)

RTL Schematic:

JK Flipflop:
module JK_FF(output q,qb, input j,k,clk);
reg q=0;
always@(posedge clk)
case({j,k})
 2'b00: q<=q;
 2'b01: q<=0;
 2'b10: q<=1;
 2'b11: q<=~q;
endcase
assign qb=~q;
endmodule

D Flipflop:
module D_FF(input d,clk, rst,output reg q,qb);
 always@(posedge clk)
 begin
 if(rst==1'b1)
 begin
 q<=1'b0;qb<=1'b1;
 end
 else
 begin
 q<=d;qb<=~d;
 end
end
endmodule

Testbench Simulation:

JK Flipflop:
module test_jkff();
reg j,k,clk=0;
always #10 clk=~clk;
JK_FF DUT(q,qb,j,k,clk);
initial begin
j<=0;k<=0;#5;
j<=0;k<=1;#20;
j<=1;k<=0;#20;
j<=1;k<=1;#20;
$finish;
end
endmodule

D Flipflop:
module test_dff();
wire q,qb;
reg d,clk,rst;
D_FF DUT(d,clk,rst,q,qb);
initial begin
clk=1'b0;
rst=1'b0;
d=1'b0;
end
always #5 clk=~clk;
always #10 d=~d;
always #10 rst=~rst;
endmodule

Experiment 6:(Design and simulation of modulo counter using Verilog behavioral modeling. Design modulo counter using JK flip-flops.)

RTL Schematic:

module counter_mod6 ( clk ,reset ,dout );
output [2:0] dout ;
reg [2:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0;
always @ (posedge (clk)) begin
 if (reset)
 dout <= 0;
 else if (dout<5)
 dout <= dout + 1;
 else
 dout <= 0;
end
endmodule

Testbench Simulation:

module counter_testbench();
reg clk, reset;
wire [2:0] counter;
counter_mod6 dut(clk, reset, counter);
initial begin
clk=0;
forever #5 clk=~clk;
end
initial begin
reset=1;
#20;
reset=0;
end
endmodule

Experiment 7:(Design and simulation of a pseudo random sequence generator in Verilog. Implementation of pseudo random sequence generator using shift register)

RTL Schematic:

module sequence_gen(op,clk);
input clk;
output [3:0]op;
reg [3:0]op;
initial
begin
op[3:0] = 4'b1100 ;
end
always @( posedge clk)
op <= {op[3]^op[1], op[3:1]};
endmodule

Testbench Simulation:

module test_sequence_gen();
reg clk;
wire [3:0] op;
sequence_gen SG1 (op,clk);
initial
begin
clk=0;
forever #10 clk = ~clk;
end
initial
begin
#200
$finish;
end
endmodule

Experiment 8:(Design and simulation of a finite state machine in Verilog to detect a given sequence of bits)

RTL Schematic:

module Seq_Det (input clk, input rst, input Din, output Dout);
reg [1:0] state;
reg Dout;
initial
begin
state <= 2'b00;
end
always @ ( posedge clk, rst )
begin
if ( rst )
state <= 2'b00;
else
begin
case( {state,Din} )
3'b000: begin
state <= 2'b00;
end
3'b001: begin
state <= 2'b01;
end
3'b010: begin
state <= 2'b10;
end
3'b011: begin
state <= 2'b01;
end
3'b100: begin
state <= 2'b10;
end
3'b101: begin
state <= 2'b11;
end
3'b110: begin
state <= 2'b10;
end
3'b111: begin
state <= 2'b01;
end
endcase
end
assign Dout = (({state,Din}) == 3'b111) ? 1'b1 : 1'b0 ;
end
endmodule

Testbench Simulation:

module test_Seq_Det();
reg clk, rst, Din;
wire Dout;
Seq_Det det1 (clk, rst, Din, Dout);
initial
begin
clk=0;
forever #10 clk = ~clk;
end
initial
begin
rst = 0;
Din = 0; #20
Din = 1; #20
Din = 0; #20
Din = 1; #20
Din = 1; #20
Din = 0; #20
Din = 1; #20
Din = 1; #20
Din = 0; #20
Din = 0; #20
Din = 0; #20
Din = 1; #20
$finish;
end
endmodule